Using L1 cache as re-order buffer

ABSTRACT

A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the L2 cache may be returned out of order, the L1 cache uses it&#39;s cache memory to buffer the out of order data and provides the data to the requesting processor in the correct order from the buffer.

This application: is a divisional of U.S. patent application Ser. No. 14/335,351, filed Jul. 18, 2014.

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is digital data processing, and more specifically cache memories.

BACKGROUND OF THE INVENTION

In a digital signal processor having both level 1 instruction (L1), level 1 data (L1D) and level 2 (L2) cache memories, there is no guarantee that when the CPU requests data from the L2 cache the data will be returned in the order of the requests. This necessitates an additional step in the L1 cache to reorder the data before providing it to the CPU. This reordering has usually been done by a reorder buffer. In high performance processors the size of this buffer may grow to an unacceptable size as the allowable outstanding memory requests and packet sizes increase. The size of the reorder buffer has a direct impact on the frequency of operation of the high performance processor and also results in increased area for the core proportional to the size of the buffer.

SUMMARY OF THE INVENTION

A method is shown that eliminates the need for a dedicated reorder buffer to guarantee that the CPU requests are serviced in the correct order. Instead, the existing L1 cache memory is reused to fulfill the function of the reorder buffer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of this invention are illustrated in the drawings, in which:

FIG. 1 illustrates a single core scalar processor according to one embodiment of this invention;

FIG. 2 illustrates a dual core scalar processor according to another embodiment of this invention;

FIG. 3 illustrates a single core vector processor according to a further embodiment of this invention;

FIG. 4 illustrates a dual core vector processor according to a further embodiment of this invention;

FIG. 5 illustrates construction of one embodiment of the CPU of this invention;

FIG. 6 illustrates the global scalar register file;

FIG. 7 illustrates global vector register file;

FIG. 8 illustrates the local vector register file shared by the multiply and correlation functional units;

FIG. 9 illustrates local register file of the load/store unit;

FIG. 10 illustrates the predicate register file;

FIG. 11 illustrates the pipeline phases of the central processing unit according to a preferred embodiment of this invention;

FIG. 12 illustrates sixteen instructions of a single fetch packet;

FIG. 13 illustrates an example of the instruction coding of instructions used by this invention;

FIG. 14 illustrates the carry control for SIMD operations according to this invention;

FIG. 15 illustrates the L1I cache microarchitecture.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates a single core scalar processor according to one embodiment of this invention. Single core processor 100 includes a scalar central processing unit (CPU) 110 coupled to separate level one instruction cache (L1I) 111 and level one data cache (L1D) 112. Central processing unit core 110 could be constructed as known in the art and would typically include a register file, an integer arithmetic logic unit, an integer multiplier and program flow control units. Single core processor 100 includes a level two combined instruction/data cache (L2) 113 that holds both instructions and data. In the preferred embodiment scalar central processing unit (CPU) 110, level one instruction cache (L1I) 111, level one data cache (L1D) 112 and level two combined instruction/data cache (L2) 113 are formed on a single integrated circuit.

In a preferred embodiment this single integrated circuit also includes auxiliary circuits such as power control circuit 121, emulation/trace circuits 122, design for test (DST) programmable built-in self test (PBIST) circuit 123 and clocking circuit 124. External to CPU 110 and possibly integrated on single integrated circuit 100 is an L3 shared memory controller core 131.

CPU 110 operates under program control to perform data processing operations upon defined data. The program controlling CPU 110 consists of a plurality of instructions that must be fetched before decoding and execution. Single core processor 100 includes a number of cache memories. FIG. 1 illustrates a pair of first level caches. Level one instruction cache (L1I) 111 stores instructions used by CPU 110. CPU 110 first attempts to access any instruction from level one instruction cache 121. Level one data cache (L1D) 112 stores data used by CPU 110. CPU 110 first attempts to access any required data from level one data cache 112. The two level one caches L1I 111 and L1D 112) are backed by a level two unified cache (L2) 113. In the event of a cache miss to level one instruction cache 111 or to level one data cache 112, the requested instruction or data is sought from level two unified cache 113. If the requested instruction or data is stored in level two unified cache 113, then it is supplied to the requesting level one cache for supply to central processing unit core 110. As is known in the art, the requested instruction or data may be simultaneously supplied to both the requesting cache and CPU 110 to speed use.

Level two unified cache 113 is further coupled to higher level memory systems via a shared L3 memory controller 131. Memory controller 131 handles cache misses in level two unified cache 113 by accessing external memory (not shown in FIG. 1). Memory controller 131 handles all memory centric functions such as cacheabilty determination, error detection and correction, address translation and the like. Single core processor 100 may be a part of a multiprocessor system. In that case memory controller 131 handles data transfer between processors and maintains cache coherence among processors.

FIG. 2 illustrates a dual core processor according to another embodiment of this invention. Dual core processor 200 includes first CPU 210 coupled to separate level one instruction cache (L1I) 211 and level one data cache (L1D) 212 and second CPU 220 coupled to separate level one instruction cache (L1I) 221 and level one data cache (L1D) 212. Central processing units 210 and 220 are preferably constructed similar to CPU 110 illustrated in FIG. 1. Dual core processor 200 includes a single shared level two combined instruction/data cache (L2) 231 supporting all four level one caches (L1I 211, L1D 212, L1I 221 and L1D 222). In the preferred embodiment CPU 210, level one instruction cache (L1I) 211, level one data cache (L1D) 212, CPU 220, level one instruction cache (L1I) 221, level one data cache (L1D) 222 and level two combined instruction/data cache (L2) 231 are formed on a single integrated circuit. This single integrated circuit preferably also includes auxiliary circuits such as power control circuit 241, emulation/trace circuits 242, design for test (DST) programmable built-in self test (PBIST) circuit 243 and clocking circuit 244. This single integrated circuit may also include memory controller 251.

FIGS. 3 and 4 illustrate single core and dual core processors similar to that shown respectively in FIGS. 1 and 2. FIGS. 3 and 4 differ from FIGS. 1 and 2 in showing vector central processing units. As further described below Single core vector processor 300 includes a vector CPU 310. Dual core vector processor 400 includes two vector CPUs 410 and 420. Vector CPUs 310, 410 and 420 include wider data path operational units and wider data registers than the corresponding scalar CPUs 110, 210 and 220.

Vector CPUs 310, 410 and 420 further differ from the corresponding scalar CPUs 110, 210 and 220 in the inclusion of streaming engine 313 (FIG. 3) and streaming engines 413 and 423 (FIG. 5). Streaming engines 313, 413 and 423 are similar. Streaming engine 313 transfers data from level two unified cache 313 (L2) to a vector CPU 310. Streaming engine 413 transfers data from level two unified cache 431 to vector CPU 410. Streaming engine 423 transfers data from level two unified cache 431 to vector CPU 420. In accordance with the preferred embodiment each streaming engine 313, 413 and 423 manages up to two data streams.

Each streaming engine 313, 413 and 423 transfer data in certain restricted circumstances. A stream consists of a sequence of elements of a particular type. Programs that operate on streams read the data sequentially, operating on each element in turn. Every stream has the following basic properties. The stream data have a well-defined beginning and ending in time. The stream data have fixed element size and type throughout the stream. The stream data have fixed sequence of elements. Thus programs cannot seek randomly within the stream. The stream data is read-only while active. Programs cannot write to a stream while simultaneously reading from it. Once a stream is opened the streaming engine: calculates the address; fetches the defined data type from level two unified cache; performs data type manipulation such as zero extension, sign extension, data element sorting/swapping such as matrix transposition; and delivers the data directly to the programmed execution unit within the CPU. Streaming engines are thus useful for real-time digital filtering operations on well-behaved data. Streaming engines free these memory fetch tasks from the corresponding CPU enabling other processing functions.

The streaming engines provide the following benefits. They permit multi-dimensional memory accesses. They increase the available bandwidth to the functional units. They minimize the number of cache miss stalls since the stream buffer can bypass L1D cache. They reduce the number of scalar operations required in the loop to maintain. They manage the address pointers. They handle address generation automatically freeing up the address generation instruction slots and the .D unit for other computations.

FIG. 5 illustrates construction of one embodiment of the CPU of this invention. Except where noted this description covers both scalar CPUs and vector CPUs. The CPU of this invention includes plural execution units multiply unit 511 (.M), correlation unit 512 (.C), arithmetic unit 513 (.L), arithmetic unit 514 (.S), load/store unit 515 (.D), branch unit 516 (.B) and predication unit 517 (.P). The operation and relationships of these execution units are detailed below.

Multiply unit 511 primarily performs multiplications. Multiply unit 511 accepts up to two double vector operands and produces up to one double vector result. Multiply unit 511 is instruction configurable to perform the following operations: various integer multiply operations, with precision ranging from 8-bits to 64-bits; various regular and complex dot product operations; and various floating point multiply operations; bit-wise logical operations; moves; as well as adds and subtracts. As illustrated in FIG. 5 multiply unit 511 includes hardware for four simultaneous 16 bit by 16 bit multiplications. Multiply unit 511 may access global scalar register file 521, global vector register file 522 and shared .M and C. local register 523 file in a manner described below. Forwarding multiplexer 530 mediates the data transfer between global scalar register file 521, global vector register file 522, the corresponding streaming engine and multiply unit 511.

Correlation unit 512 (.C) accepts up to two double vector operands and produces up to one double vector result. Correlation unit 512 supports these major operations. In support of WCDMA “Rake” and “Search” instructions correlation unit 512 performs up to 512 2-bit PN*8-bit I/Q complex multiplies per clock cycle. Correlation unit 512 performs 8-bit and 16-bit Sum-of-Absolute-Difference (SAD) calculations performing up to 512 SADs per clock cycle. Correlation unit 512 performs horizontal add and horizontal min/max instructions. Correlation unit 512 performs vector permutes instructions. Correlation unit 512 includes contains 8 256-bit wide control registers. These control registers are used to control the operations of certain correlation unit instructions. Correlation unit 512 may access global scalar register file 521, global vector register file 522 and shared .M and C. local register file 523 in a manner described below. Forwarding multiplexer 530 mediates the data transfer between global scalar register file 521, global vector register file 522, the corresponding streaming engine and correlation unit 512.

CPU 500 includes two arithmetic units: arithmetic unit 513 (.L) and arithmetic unit 514 (.S). Each arithmetic unit 513 and arithmetic unit 514 accepts up to two vector operands and produces one vector result. The compute units support these major operations. Arithmetic unit 513 and arithmetic unit 514 perform various single-instruction-multiple-data (SIMD) fixed point arithmetic operations with precision ranging from 8-bit to 64-bits. Arithmetic unit 513 and arithmetic unit 514 perform various vector compare and minimum/maximum instructions which write results directly to predicate register file 526 (further described below). These comparisons include A=B, A>B, A≧B, A<B and A≦B. If the comparison is correct, a 1 bit is stored in the corresponding bit position within the predicate register. If the comparison fails, a 0 is stored in the corresponding bit position within the predicate register. Vector compare instructions assume byte (8 bit) data and thus generate 32 single bit results. Arithmetic unit 513 and arithmetic unit 514 perform various vector operations using a designated predicate register as explained below. Arithmetic unit 513 and arithmetic unit 514 perform various SIMD floating point arithmetic operations with precision ranging from half-precision (16-bits), single precision (32-bits) to double precision (64-bits). Arithmetic unit 513 and arithmetic unit 514 perform specialized instructions to speed up various algorithms and functions. Arithmetic unit 513 and arithmetic unit 514 may access global scalar register file 521, global vector register file 522, shared .L and .S local register file 524 and predicate register file 526. Forwarding multiplexer 530 mediates the data transfer between global scalar register file 521, global vector register file 522, the corresponding streaming engine and arithmetic units 513 and 514.

Load/store unit 515 (.D) is primarily used for address calculations. Load/store unit 515 is expanded to accept scalar operands up to 64-bits and produces scalar result up to 64-bits. Load/store unit 515 includes additional hardware to perform data manipulations such as swapping, pack and unpack on the load and store data to reduce workloads on the other units. Load/store unit 515 can send out one load or store request each clock cycle along with the 44-bit physical address to level one data cache (L1D). Load or store data width can be 32-bits, 64-bits, 256-bits or 512-bits. Load/store unit 515 supports these major operations: 64-bit SIMD arithmetic operations; 64-bit bit-wise logical operations; and scalar and vector load and store data manipulations. Load/store unit 515 preferably includes a micro-TLB (table look-aside buffer) block to perform address translation from a 48-bit virtual address to a 44-bit physical address. Load/store unit 515 may access global scalar register file 521, global vector register file 522 and .D local register file 525 in a manner described below. Forwarding multiplexer 530 mediates the data transfer between global scalar register file 521, global vector register file 522, the corresponding streaming engine and load/store unit 515.

Branch unit 516 (.B) calculates branch addresses, performs branch predictions, and alters control flows dependent on the outcome of the prediction.

Predication unit 517 (.P) is a small control unit which performs basic operations on vector predication registers. Predication unit 517 has direct access to the vector predication registers 526. Predication unit 517 performs different bit operations on the predication registers such as AND, ANDN, OR, XOR, NOR, BITR, NEG, SET, BITCNT (bit count), RMBD (right most bit detect), BIT Decimate and Expand, etc.

FIG. 6 illustrates global scalar register file 521. There are 16 independent 64-bit wide scalar registers. Each register of global scalar register file 521 can be read as 32-bits scalar data (designated registers A0 to A15 601) or 64-bits of scalar data (designated registers EA0 to EA15 611). However, writes are always 64-bit, zero-extended to fill up to 64-bits if needed. All scalar instructions of all functional units can read or write to global scalar register file 521. The instruction type determines the data size. Global scalar register file 521 supports data types ranging in size from 8-bits through 64-bits. A vector instruction can also write to the 64-bit global scalar registers 521 with the upper 192 bit data of the vector discarded. A vector instruction can also read 64-bit data from the global scalar register file 511. In this case the operand is zero-extended in the upper 192-bit to form an input vector.

FIG. 7 illustrates global vector register file 522. There are 16 independent 256-bit wide vector registers. Each register of global vector register file 522 can be read as 32-bits scalar data (designated registers X0 to X15 701), 64-bits of scalar data (designated registers EX0 to EX15 711), 256-bit vector data (designated registers VX0 to VX15 721) or 512-bit double vector data (designated DVX0 to DVX7, not illustrated). In the current embodiment only multiply unit 511 and correlation unit 512 may execute double vector instructions. All vector instructions of all functional units can read or write to global vector register file 522. Any scalar instruction of any functional unit can also access the low 32 or 64 bits of a global vector register file 522 register for read or write. The instruction type determines the data size.

FIG. 8 illustrates local vector register file 523. There are 16 independent 256-bit wide vector registers. Each register of local vector register file 523 can be read as 32-bits scalar data (designated registers M0 to M15 701), 64-bits of scalar data (designated registers EM0 to EM15 711), 256-bit vector data (designated registers VM0 to VM15 721) or 512-bit double vector data (designated DVM0 to DVM7, not illustrated). In the current embodiment only multiply unit 511 and correlation unit 512 may execute double vector instructions. All vector instructions of all functional units can write to local vector register file 523. Only instructions of multiply unit 511 and correlation unit 512 may read from local vector register file 523. The instruction type determines the data size.

Multiply unit 511 may operate upon double vectors (512-bit data). Multiply unit 511 may read double vector data from and write double vector data to global vector register file 521 and local vector register file 523. Register designations DVXx and DVMx are mapped to global vector register file 521 and local vector register file 523 as follows.

TABLE 1 Instruction Register Designation Accessed DVX0 VX1:VX0 DVX1 VX3:VX2 DVX2 VX5:VX4 DVX3 VX7:VX6 DVX4 VX9:VX8 DVX5 VX11:VX10 DVX6 VX13:VX12 DVX7 VX15:VX14 DVM0 VM1:VM0 DVM1 VM3:VM2 DVM2 VM5:VM4 DVM3 VM7:VM6 DVM4 VM9:VM8 DVM5 VM11:VM10 DVM6 VM13:VM12 DVM7 VM15:VM14

Each double vector designation maps to a corresponding pair of adjacent vector registers in either global vector register 522 or local vector register 523. Designations DVX0 to DVX7 map to global vector register 522. Designations DVM0 to DVM7 map to local vector register 523.

Local vector register file 524 is similar to local vector register file 523. There are 16 independent 256-bit wide vector registers. Each register of local vector register file 524 can be read as 32-bits scalar data (designated registers L0 to L15 701), 64-bits of scalar data (designated registers EL0 to EL15 711) or 256-bit vector data (designated registers VL0 to VL15 721). All vector instructions of all functional units can write to local vector register file 524. Only instructions of arithmetic unit 513 and arithmetic unit 514 may read from local vector register file 524.

FIG. 9 illustrates local register file 525. There are 16 independent 64-bit wide registers. Each register of local register file 525 can be read as 32-bits scalar data (designated registers D0 to D15 701) or 64-bits of scalar data (designated registers ED0 to ED15 711). All scalar and vector instructions of all functional units can write to local register file 525. Only instructions of load/store unit 515 may read from local register file 525. Any vector instructions can also write 64-bit data to local register file 525 with the upper 192 bit data of the result vector discarded. Any vector instructions can also read 64-bit data from the 64-bit local register file 525 registers. The return data is zero-extended in the upper 192-bit to form an input vector. The registers of local register file 525 can only be used as addresses in load/store instructions, not as store data or as sources for 64-bit arithmetic and logical instructions of load/store unit 515.

FIG. 10 illustrates the predicate register file 526. There are sixteen registers 32-bit registers in predicate register file 526. Predicate register file 526 contains the results from vector comparison operations and is used by vector selection instructions and vector predicated store instructions. A small subset of special instructions can also read directly from predicate registers, performs operations and write back to a predicate register directly. There are also instructions which can transfer values between the global register files (521 and 522) and predicate register file 526. Transfers between predicate register file 526 and local register files (523, 524 and 525) are not supported. Each bit of a predication register (designated P0 to P15) controls a byte of a vector data. Since a vector is 256-bits, the width of a predicate register equals 256/8=32 bits. The predicate register file can be written to by vector comparison operations to store the results of the vector compares.

A CPU such as CPU 110, 210, 220, 310, 410 or 420 operates on an instruction pipeline. This instruction pipeline can dispatch up to nine parallel 32-bits slots to provide instructions to the seven execution units (multiply unit 511, correlation unit 512, arithmetic unit 513, arithmetic unit 514, load/store unit 515, branch unit 516 and predication unit 517) every cycle. Instructions are fetched instruction packets of fixed length further described below. All instructions require the same number of pipeline phases for fetch and decode, but require a varying number of execute phases.

FIG. 11 illustrates the following pipeline phases: program fetch phase 1110, dispatch and decode phases 1120 and execution phases 1130. Program fetch phase 1110 includes three stages for all instructions. Dispatch and decode phases 1120 include three stages for all instructions. Execution phase 1130 includes one to four stages dependent on the instruction.

Fetch phase 1110 includes program address generation stage 1111 (PG), program access stage 1112 (PA) and program receive stage 1113 (PR). During program address generation stage 1111 (PG), the program address is generated in the CPU and the read request is sent to the memory controller for the level one instruction cache L1I. During the program access stage 1112 (PA) the level one instruction cache L1I processes the request, accesses the data in its memory and sends a fetch packet to the CPU boundary. During the program receive stage 1113 (PR) the CPU registers the fetch packet.

Instructions are always fetched sixteen words at a time. FIG. 12 illustrates this fetch packet. FIG. 12 illustrates 16 instructions 1201 to 1216 of a single fetch packet. Fetch packets are aligned on 512-bit (16-word) boundaries. The execution of the individual instructions is partially controlled by a p bit in each instruction. This p bit is preferably bit 0 of the instruction. The p bit determines whether the instruction executes in parallel with another instruction. The p bits are scanned from lower to higher address. If the p bit of an instruction is 1, then the next following instruction is executed in parallel with (in the same cycle as) that instruction I. If the p bit of an instruction is 0, then the next following instruction is executed in the cycle after the instruction. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to nine instructions. Each instruction in an execute packet must use a different functional unit. An execute packet can contain up to nine 32-bit wide slots. A slot can either be a self-contained instruction or expand the constant field specified by the immediate preceding instruction. A slot can be used as conditional codes to apply to the instructions within the same fetch packet. A fetch packet can contain up to 2 constant extension slots and one condition code extension slot.

There are up to 11 distinct instruction slots, but scheduling restrictions limit to 9 the maximum number of parallel slots. The maximum nine slots are shared as follows: multiply unit 511; correlation unit 512; arithmetic unit 513; arithmetic unit 514; load/store unit 515; branch unit 516 shared with predicate unit 517; a first constant extension; a second constant extension; and a unit less instruction shared with a condition code extension. The last instruction in an execute packet has a p bit equal to 0.

The CPU and level one instruction cache L1I pipelines are de-coupled from each other. Fetch packet returns from level one instruction cache L1I can take different number of clock cycles, depending on external circumstances such as whether there is a hit in level one instruction cache L1I. Therefore program access stage 1112 (PA) can take several clock cycles instead of 1 clock cycle as in the other stages.

Dispatch and decode phases 1120 include instruction dispatch to appropriate execution unit stage 1121 (DS), instruction pre-decode stage 1122; (DC1); and instruction decode, operand reads stage 1123 (DC2). During instruction dispatch to appropriate execution unit stage 1121 (DS) the fetch packets are split into execute packets and assigned to the appropriate functional units. During the instruction pre-decode stage 1122 (DC1) the source registers, destination registers, and associated paths are decoded for the execution of the instructions in the functional units. During the instruction decode, operand reads stage 1123 (DC2) more detail unit decodes are done, as well as reading operands from the register files.

Execution phases 1130 includes execution stages 1131 to 1135 (E1 to E5). Different types of instructions require different numbers of these stages to complete their execution. These stages of the pipeline play an important role in understanding the device state at CPU cycle boundaries.

During execute 1 stage 1131 (E1) the conditions for the instructions are evaluated and operands are operated on. As illustrated in FIG. 11, execute 1 stage 1131 may receive operands from a stream buffer 1141 and one of the register files shown schematically as 1142. For load and store instructions, address generation is performed and address modifications are written to a register file. For branch instructions, branch fetch packet in PG phase is affected. As illustrated in FIG. 11, load and store instructions access memory here shown schematically as memory 1151. For single-cycle instructions, results are written to a destination register file. This assumes that any conditions for the instructions are evaluated as true. If a condition is evaluated as false, the instruction does not write any results or have any pipeline operation after execute 1 stage 1131.

During execute 2 stage 1132 (E2) load instructions send the address to memory. Store instructions send the address and data to memory. Single-cycle instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For 2-cycle instructions, results are written to a destination register file.

During execute 3 stage 1133 (E3) data memory accesses are performed. Any multiply instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For 3-cycle instructions, results are written to a destination register file.

During execute 4 stage 1134 (E4) load instructions bring data to the CPU boundary. For 4-cycle instructions, results are written to a destination register file.

During execute 5 stage 1135 (E5) load instructions write data into a register. This is illustrated schematically in FIG. 11 with input from memory 1151 to execute 5 stage 1135.

FIG. 13 illustrates an example of the instruction coding of instructions used by this invention. Each instruction consists of 32 bits and controls the operation of one of the individually controllable functional units (multiply unit 511, correlation unit 512, arithmetic unit 513, arithmetic unit 514, load/store unit 515). The bit fields are defined as follows. The creg field and the z bit are optional fields used in conditional instructions. These bits are used for conditional instructions to identify the predicate register and the condition. The z bit (bit 28) indicates whether the predication is based upon zero or not zero in the predicate register. If z=1, the test is for equality with zero. If z=0, the test is for nonzero. The case of creg=0 and z=0 is treated as always true to allow unconditional instruction execution. The creg field and the z field are encoded in the instruction as shown in Table 2.

TABLE 2 Conditional Register creg z 31 30 29 28 Unconditional 0 0 0 0 Reserved 0 0 0 1 A0 0 0 1 z A1 0 1 0 z A2 0 1 1 z A3 1 0 0 z A4 1 0 1 z A5 1 1 0 z Reserved 1 1 x x

Note that “z” in the z bit column refers to the zero/not zero comparison selection noted above and “x” is a don't care state. This coding can only specify a subset of the 16 global scalar registers as predicate registers. This selection was made to preserve bits in the instruction coding. Note that unconditional instructions do not have these optional bits. For unconditional instructions these bits (28 to 31) are preferably used as additional opcode bits. However, if needed, an execute packet can contain a unique 32-bit condition code extension slot which contains the 4-bit CREGZ fields for the instructions which are in the same execute packet. Table 3 shows the coding of such a condition code extension slot.

TABLE 3 Bits Functional Unit 3:0 .L 7:4 .S 11:5  .D 15:12 .M 19:16 .C 23:20 .B 28:24 Reserved 31:29 Reserved Thus the condition code extension slot specifies bits decoded in the same way the creg/z bits assigned to a particular functional unit in the same execute packet.

Special vector predicate instructions use the designated predicate register to control vector operations. In the current embodiment all these vector predicate instructions operate on byte (8 bit) data. Each bit of the predicate register controls whether a SIMD operation is performed upon the corresponding byte of data. The operations of predicate unit 517 permit a variety of compound vector SIMD operations based upon more than one vector comparison. For example a range determination can be made using two comparisons. A candidate vector is compared with a first vector reference having the minimum of the range packed within a first data register. A second comparison of the candidate vector is made with a second reference vector having the maximum of the range packed within a second data register. Logical combinations of the two resulting predicate registers would permit a vector conditional operation to determine whether each data part of the candidate vector is within range or out of range.

The dst field specifies a register in a corresponding register file as the destination of the instruction results.

The src2 field specifies a register in a corresponding register file as the second source operand.

The src1/cst field has several meanings depending on the instruction opcode field (bits 2 to 12 and additionally bits 28 to 31 for unconditional instructions). The first meaning specifies a register of a corresponding register file as the first operand. The second meaning is an immediate constant. Depending on the instruction type, this is treated as an unsigned integer and zero extended to a specified data length or is treated as a signed integer and sign extended to the specified data length.

The opcode field (bits 2 to 12 for all instructions and additionally bits 28 to 31 for unconditional instructions) specifies the type of instruction and designates appropriate instruction options. This includes designation of the functional unit and operation performed. A detailed explanation of the opcode is beyond the scope of this invention except for the instruction options detailed below.

The p bit (bit 0) marks the execute packets. The p-bit determines whether the instruction executes in parallel with the following instruction. The p-bits are scanned from lower to higher address. If p=1 for the current instruction, then the next instruction executes in parallel with the current instruction. If p=0 for the current instruction, then the next instruction executes in the cycle after the current instruction. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to eight instructions. Each instruction in an execute packet must use a different functional unit.

Correlation unit 512 and arithmetic units 513 and 514 often operate in a single instruction multiple data (SIMD) mode. In this SIMD mode the same instruction is applied to packed data from the two operands. Each operand holds plural data elements disposed in predetermined slots. SIMD operation is enabled by carry control at the data boundaries. Such carry control enables operations on varying data widths.

FIG. 14 illustrates the carry control. AND gate 1401 receives the carry output of bit N within the operand wide arithmetic logic unit (256 bits for arithmetic units 513 and 514, 512 bits for correlation unit 512). AND gate 1401 also receives a carry control signal which will be further explained below. The output of AND gate 1401 is supplied to the carry input of bit N+1 of the operand wide arithmetic logic unit. AND gates such as AND gate 1401 are disposed between every pair of bits at a possible data boundary. For example, for 8-bit data such an AND gate will be between bits 7 and 8, bits 15 and 16, bits 23 and 24, etc. Each such AND gate receives a corresponding carry control signal. If the data size is of the minimum, then each carry control signal is 0, effectively blocking carry transmission between the adjacent bits. The corresponding carry control signal is 1 if the selected data size requires both arithmetic logic unit sections. Table 4 below shows example carry control signals for the case of a 256 bit wide operand such as used in arithmetic units 513 and 514 which may be divided into sections of 8 bits, 16 bits, 32 bits, 64 bits or 128 bits. No control of the carry output of the most significant bit is needed, thus only 31 carry control signals are required.

TABLE 4 Data Size Carry Control Signals  8 bits −000 0000 0000 0000 0000 0000 0000 0000 16 bits −101 0101 0101 0101 0101 0101 0101 0101 32 bits −111 0111 0111 0111 0111 0111 0111 0111 64 bits −111 1111 0111 1111 0111 1111 0111 1111 128 bits  −111 1111 1111 1111 0111 1111 1111 1111 256 bits  −111 1111 1111 1111 1111 1111 1111 1111 It is typical in the art to operate on data sizes that are integral powers of 2 (2^(N)). However, this carry control technique is not limited to integral powers of 2. One skilled in the art would understand how to apply this technique to other data sizes and other operand widths.

FIG. 15 shows the micro architecture of the Program Memory Controller (PMC). On accepting a new request from CPU 1501, PMC does a tag look up in tag RAM 1502 in the first pipe stage and registers both the address and fetch packet count for use by the prefetch FSM 1504 to generate additional requests to the tag RAM 1502. A third access to the tag RAM 1502 is also possible whenever return data from UMC 1503 is present on the L1I-L2 interface. This return data takes highest priority in tag RAM 1502 access and is written immediately. The second priority goes to a newly accepted request on the CPU-L1I interface, with the least priority given to requests initiated by the prefetch Finite State Machine (FSM) 1504. L1I never accepts a new CPU request whenever there are pending requests in the prefetch state machine 1504; this ensures the population of scoreboard 1506 after tag lookup is in the same order as requested by CPU.

L1I does a tag compare in 1507 of all four (4) cache ways with the new request to determine a hit or miss. L1I also uses the registered branch address and “fetch packet count—fp_cnt” to determine page translation in the uTLB 1505. Whenever a new request is determined by L1I to span two pages, L1I sends a request for the first page and queues up a second (prefetch) request to the uTLB 1505 for the second page immediately. This enables L1I to hide some of the latency due to uTLB 1505 misses. L1I achieves this by adding “fp_cnt*line_size” to the branch address given by CPU 1501 and checking if it falls within the same page as the branch address. If not, the prefetch request to uTLB 1505 is generated.

To facilitate efficient allocation and accurate ordering of data response to CPU, L1I always allocates valid entries to the Tag RAM 1502 regardless of ordering and uses an 8 deep scoreboard 1506 to track and process all outstanding requests. Whenever a new request has been processed through pipe stages 1 and 2, and a cache hit/miss has been determined, the new request is allocated to the scoreboard 1506 with a CID, virtual address, physical address, way and hit/miss information. The transaction ID (CID) is used to map responses to specific entries in the scoreboard along with re-ordering out-of-order responses from L2. The CID also provides index to the virtual address which is used for tag and data allocation on data return from L2. This virtual address is sent along with data and parity information to CPU 1501. The way information is used to determine data RAM 1508 read address for accesses due to hits or re-ordering, and for tag ram RAM 1502 and data RAM 1508 allocation whenever there is return data from L2. The hit/miss information is used to determine if a request will be processed from L1I cache or sent as a miss to L2.

The scoreboard 1506 also enables the aggregation of two entries to a single one if the second entry is a 64 byte offset from the first and the two request are to even and odd sets consecutively. For example, if a branch address mapping to set2 and “fp_cnt” of 2 is requested, the two requests generated are merged to a single one in the scoreboard 1506 because they are consecutive 64 byte requests from the same base address starting with the even set first. On the contrary, if the branch address maps to set1 and the same “fp_cnt” of 2 is requested, then the 2 requests generated cannot be merged. This is because the 1st first dataphase returned maps to set0 which was not requested and is therefore dropped while the second dataphase satisfies the 1st request for set1. A separate request for set2 has to be queued to L2, the first dataphase returned satisfies the request for the set2 address while the second dataphase which maps to unrequested set3 is also cached as a prefetched entry. If the current return data from L2 is the next to be processed to CPU 1501, L1I registers and sends this data to CPU 1501 directly in the same cycle it is being allocated to the data RAM 1508 to avoid a second data RAM 1508 access.

On a CPU 1501 flush request, L1I invalidates all scoreboard entries and advances the CID to the next miss CID planned to be sent to L2. This ensures efficient usage of CIDs and enables seamless processing (dropping) of return data for flushed entries. Any return data which has been placed on the CPU-Program Memory Controller (PMC) interface but not already accepted by CPU 1501 before a flush occurs is kept on the interface until CPU 1501 accepts the data.

The DSP of this invention preferably has a program memory controller (L1I controller) and a Unified L2 Memory Controller (UMC). In the L1I to L2 interface, the return data from L2 can be returned out of order. It is the responsibility of the L1I controller to return the requests in order to the CPU.

In the previous generation C66x DSP from Texas Instruments, a maximum of 3 outstanding requests were allowed from L1 to L2, with a fetch packet size of 32 bytes. Two 32 byte registers were incorporated in the C66x DSP to function as reorder buffers that returned data in order to the CPU.

In DSP of this invention the fetch packet size was increased to 84 bytes, and up to 8 outstanding requests to L2 were allowed. A reorder buffer would require significant register or memory size to store the requests and return them to the CPU in order.

A more efficient approach is to reuse the L1I cache itself as the reorder buffer.

A scoreboard 1506 in L1I controller tracks the order in which requests need to be returned to CPU. L2 return data gets allocated into the L1I cache.

Whenever data is returned from UMC 1503, the scoreboard 1506 is consulted to check if it is the request that needs to be sent to CPU 1501. If yes, it is sent directly to CPU 1501 and allocated into the L1I cache. If it is not the request that has to be sent to CPU (out of order transaction), then it is allocated into the L1I cache and the scoreboard 1506 is updated to indicate that it is available in the cache. Once the CPU request in order is serviced, if the next request is available in the L1I cache, it is returned by reading it from the cache. Whenever there is a new return data from CPU, the scoreboard 1506 is consulted in parallel to identify if the next data is already present in the cache. If it is, then a data RAM 1508 read is scheduled immediately so that there are no additional stalls inserted due to the data RAM read. The data RAM is arbitrated for write allocates and L1I hits. This a-priori read minimizes the stall between back to back data return to CPU by prioritizing CPU read over L1I hits and write allocates. 

What is claimed is:
 1. A data processing system comprising: a central processing unit capable of generating memory data requests; a cache temporarily storing memory data for use by the central processing unit; a scoreboard connected to said central processing unit and said cache, said scoreboard operating to store an ordered list of entries of pending memory data requests received from said central processing unit, said scoreboard operable to track outstanding requests, initiating an entry upon receiving a memory data request from said central processing unit and retiring an entry upon providing corresponding requested data to said central processing unit, verify if the data in response to an oldest pending data request is available in said cache: if so providing the data to said central processing unit from said cache, and if not requesting the data from external memory, upon receiving data returned from the external memory in response to a memory data request, verify that the returned data is in response to the oldest pending data request: if so providing the data to said central processing unit, and if not storing the returned data in said cache and indicating that the received data is available in said cache.
 2. The data processing system of claim 1, wherein: said scoreboard verifies the presence of the returned data in said cache in parallel with receiving the data thus eliminating cache stalls.
 3. The data processing system of claim 1, wherein: each entry in said scoreboard contains a transaction ID (CID), a virtual address, a physical address, a cache way, and cache hit/miss information.
 4. The data processing system of claim 3, wherein: said scoreboard operates to map received data from the external memory to data requests previously entered into the scoreboard by sequence information contained in the CID.
 5. The data processing system of claim 3, wherein: said scoreboard operates to reorder data received out of order using sequence information contained in the CID.
 6. The data processing system of claim 1, wherein: said scoreboard operates to merge two scoreboard entries into one entry if the second scoreboard entry's address is on a 64 byte offset from the first scoreboard entry's address and the data requests are for consecutive even and odd cache sets.
 7. The data processing system of claim 1, wherein: said scoreboard operates to invalidate all scoreboard entries and advance the CID upon receiving a cache flush request. 